View L6599ATD_7267515.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 2009 doc id 15534 rev 3 1/31 31 l6599at improved high-voltage resonant controller features 50% duty cycle, variable frequency control of resonant half-bridge high-accuracy oscillator up to 500 khz operating frequency two-level ocp: frequency-shift and latched shutdown interface with pfc controller latched disable input burst-mode operation at light load input for power-on/off sequencing or brownout protection non-linear soft-start for monotonic output voltage rise 600 v-rail compatible high-side gate driver with integrated bootstrap diode and high dv/dt immunity -300/700 ma high-side and low-side gate drivers with uvlo pull-down dip16, so16n package guaranteed for extreme temperature ranges applications street lighting lcd and pdp tvs desktop pcs, entry-level servers telecom smps high efficiency industrial smps ac-dc adapters, open frame smps dip16 so16n table 1. device summary order codes package packaging L6599ATD so16n tube L6599ATDtr so16n tape and reel l6599atn dip16 tube www.st.com
contents l6599at 2/31 doc id 15534 rev 3 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 current sense, ocp and olp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
l6599at device description doc id 15534 rev 3 3/31 1 device description the l6599at is a temperature-extended version of the l6599a. it is a double-ended controller specifically designed for the series -resonant half-bridge topology. it provides a 50% complementary duty cycle: the high-side switch and the low-side switch are driven on/off at 180 out-of-phase for exactly the same time interval. output voltage regulation is obtained by modulating the operating frequency. a fixed dead-time inserted between the turn-off of one switch and the turn-on of the other guarantees soft-switching and enables high-frequency operation. to drive the high-side switch using the bootstrap approach, the ic incorporates a high- voltage floating structure capable of withstanding more than 600 v with a synchronous- driven high-voltage dmos that replaces the external fast-recovery bootstrap diode. the ic enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator. at start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. this frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well. at light load the ic may enter a controlled burst-mode operation that keeps the converter input consumption to a minimum. the device?s functions include a not-latched acti ve-low disable input with current hysteresis suitable for power sequencing or for brownout protection, a current sense input for ocp with frequency shift and delayed shutdown with automatic restart. a higher level ocp latches off the ic if the first-level protection is not sufficient to control the primary current. their combination offers complete protection against overload and short-circuits. an additional latched disable input (dis) allows easy implementation of otp and/or ovp. an interface with the pfc controller is provided that enables the switching off of the pre- regulator during fault conditions, such as ocp shutdown and dis high, or during burst- mode operation.
block diagram l6599at 4/31 doc id 15534 rev 3 2 block diagram figure 1. block diagram 9ff 9 %227 +9 ',6$%/( ',6 287 & %227 /&7$1. &,5&8,7 89 '(7(&7,21 9ff +9* 6<1&+521286 %227675$3 ',2'( +9* '5,9(5 ',6 /(9(/ 6+,)7(5 9 64 5 89/2 89/ 2 ',6 9 9 67$1'%< 67%< '5,9,1* *1' ,iplq ,6(1 9 /9* /9* '5,9(5 &vv '($' 7,0( 5)pl q 46 5 89/2 ,6(1b',6 '5,9,1* /2*,& 9 67$1'%< ',6 ,6(1b',6 9 3)&b6723 &) &21752/ /2*,& /,1(b2. 9 ?$ 9 2&3 9&2 /,1( '(/$< !-v
l6599at pin connection doc id 15534 rev 3 5/31 3 pin connection figure 2. pin connection (top view) table 2. pin description pin n type function 1css soft-start. this pin connects an external capacitor to gnd and a resistor to rfmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). an internal switch discharges this capacitor every time the chip turns off (vcc < uvlo, line < 1.24 v or > 6 v, dis > 1.85 v, isen > 1.5 v, delay > 2 v) to make sure it is soft-started next, and when the voltage on the current sense pin (isen) exceeds 0.8 v, as long as it stays above 0.75 v. 2delay delayed shutdown upon overcurrent. a capacitor and a resistor are connected from this pin to gnd to set the maximum duration of an overcurrent condition before the ic stops switching and the delay after which the ic restarts switching. ev ery time the voltage on the isen pin exceeds 0.8 v the capacitor is charged by an internal 150 a current generator and is slowly discharged by the external resistor. if the voltage on the pin reaches 2 v, the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 a is kept always on. as the vo ltage on the pin exceeds 3.5 v the ic stops switching and the internal generator is turned off, so that the voltage on the pin decays because of the external resistor. the ic is soft-restarted as the voltage drops below 0.3 v. in this way, under short-circuit conditions, the converter works intermittently with very low input average power. 3cf timing capacitor. a capacitor connecte d from this pin to gnd is charged and discharged by internal current generators programmed by the external network connected to pin 4 (rfmin) and determines the switching frequency of the converter. !-v '.$ #ss $%,!9 34"9 )3%. ,).% ,6' 6"//4 (6' .# 6cc 0&#?34/0 /54 $)3 #& 2&min
pin connection l6599at 6/31 doc id 15534 rev 3 4rfmin minimum oscillator frequency setting. this pin provides a precise 2 v reference and a resistor connected from this pin to gnd defines a current that is used to set the minimum oscillator frequency. to close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler is connected to this pin through a resistor. the value of this resistor sets the maximum operating frequency. an r-c series co nnected from this pin to gnd sets frequency shift at start-up to prevent excessive energy inrush (soft-start). 5stby burst-mode operation threshold. the pin senses some voltage related to the feedback control, which is compared to an internal reference (1.24 v). if the voltage on the pin is lower than the reference, the ic enters an idle state and its quiescent current is reduced. the chip restarts switching as the voltage exceeds the reference by 50 mv. soft-start is not invoked. this function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin rfmin (see block diagram). tie the pin to rfmin if burst-mode is not used. 6 isen current sense input. the pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. this input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current inform ation. as the voltage exceeds a 0.8 v threshold (with 50 mv hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. under output short-circuit, this normally results in a nearly constant peak primary current. this condition is allowed for a maximum time set at pin 2. if the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5 v latches the device off and brings its consumption almost to a ?before start-up? level. the information is latched and it is necessary to recycle the supply voltage of the ic to enable it to restart: t he latch is removed as the voltage on the vcc pin goes below the uvlo threshold. tie the pin to gnd if the function is not used. 7line line sensing input. the pin is to be connected to the high-voltage input bus with a resistor divider to perform ei ther ac or dc (in systems with pfc) brownout protection. a voltage below 1. 24 v shuts down (not latched) the ic, lowers its consumption and discharges the soft-start capacitor. ic?s operation is re-enabled (soft-started) as the voltage exceeds 1.24 v. the comparator is provided with current h ysteresis: an internal 13 a current generator is on as long as the voltage applied at the pin is below 1.24 v and is off if this value is exceeded. bypass the pin with a capacitor to gnd to reduce noise pick-up. the voltage on the pin is top-limited by an internal zener. activating the zener causes the ic to shut down (not latched). bias the pin between 1.24 and 6 v if the function is not used. 8dis latched device shutdown. internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85v, shuts the ic down and brings its consumption almost to a ?before start-up? level. the information is latched and it is necessary to recycle th e supply voltage of the ic to enable it to restart: the latch is removed as the voltage on the vcc pin goes below the uvlo threshold. tie the pin to gnd if the function is not used. table 2. pin description (continued) pin n type function
l6599at pin connection doc id 15534 rev 3 7/31 9pfc_stop open-drain on/off control of pfc cont roller. this pin, normally open, is intended for stopping the pfc controller, for protection purpose or during burst-mode operation. it goes low when the ic is shut down by dis>1.85 v, isen > 1.5 v, line > 6 v and stby< 1.24 v. the pin is pulled low also when the voltage on pin delay exceeds 2 v and goes back open as the voltage falls below 0.3 v. during uvlo, it is open. leave the pin unconnected if not used. 10 gnd chip ground. current return for both the low-side gate-drive current and the bias current of the ic. all of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 11 lvg low-side gate-drive output. the driver is capable of 0.3 a min. source and 0.7 a min. sink peak current to driv e the lower mosfet of the half-bridge leg. the pin is actively pulled to gnd during uvlo. 12 vcc supply voltage of both the signal part of the ic and the low-side gate driver. sometimes a small bypass capaci tor (0.1 f typ.) to gnd might be useful to get a clean bias voltage for the signal part of the ic. 13 n.c. high-voltage spacer. the pin is not inte rnally connected to isolate the high- voltage pin and ease compliance with safety regulations (creepage distance) on the pcb. 14 out high-side gate-drive floating ground. cu rrent return for the high-side gate- drive current. layout carefully the connection of this pin to avoid too large spikes below ground. 15 hvg high-side floating gate-drive output. t he driver is capable of 0.3 a min. source and 0.7 a min. sink peak curren t to drive the upper mosfet of the half-bridge leg. a resistor interna lly connected to pin 14 (out) ensures that the pin is not floating during uvlo. 16 vboot high-side gate-drive floating supply voltage. the bootstrap capacitor connected between this pin and pin 14 (out) is fed by an internal synchronous bootstrap diode driven in-p hase with the low-side gate-drive. this patented structure replaces the normally used external diode. table 2. pin description (continued) pin n type function
electrical data l6599at 8/31 doc id 15534 rev 3 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 14, 15 and 16 is guaranteed up to 900 v. 4.2 thermal data table 3. absolute maximum rating symbol pin parameter value unit v boot 16 floating supply voltage -1 to 618 v v out 14 floating ground voltage -3 to v boot -18 v dv out /dt 14 floating ground max. slew rate 50 v/ns vcc 12 ic supply voltage (icc = 25 ma) self-limited v v pfc_stop 9 maximum voltage (pin open) -0.3 to vcc v i pfc_stop 9 maximum sink current (pin low) self-limited a v linemax 7 maximum pin voltage (ipin 1 ma) self-limited v i rfmin 4 maximum source current 2 ma --- 1 to 6, 8 analog inputs & outputs -0.3 to 5 v ptot power dissipation @t a = 70 c (dip16) 1 w power dissipation @t a = 50 c (so16) 0.83 tj junction temperature operating range -40 to 150 c tstg storage temperature -55 to 150 c table 4. thermal data symbol parameter value unit r th(ja) max. thermal resistance junc tion-to-ambient (dip16) 80 c/w max. thermal resistance junc tion-to-ambient (so16) 120 c/w
l6599at electrical characteristics doc id 15534 rev 3 9/31 5 electrical characteristics t j = -40 to 125 c, vcc = 15 v, vb oot = 15 v, c hvg = c lvg = 1 nf; cf = 470 pf; r rfmin = 12 k ; unless otherwise specified table 5. electrical characteristics symbol parameter test condition min. typ. max. unit ic supply voltage vcc operating range after device turn-on 8.85 16 v vcc on turn-on threshold voltage rising 10 10.7 11.4 v vcc off turn-off threshold voltage falling 7.45 8.15 8.85 v hys hysteresis 2.55 v v z vcc clamp voltage iclamp = 15 ma 16 17 17.9 v supply current i start-up start-up current before device turn-on vcc = vcc on - 0.2 v 200 250 a i q quiescent current device on, v stby = 1 v 1.5 2 ma i op operating current device on, v stby = v rfmin 3.5 5 ma i q residual consumption v dis > 1.85 v or v delay > 3.5 v or v line < 1.24 v or v line = v clamp 300 400 a high-side floating gate-drive supply i lkboot v boot pin leakage current v boot = 580 v 5 a i lkout out pin leakage current v out = 562 v 5 a r ds(on) synchronous bootstrap diode on-resistance v lvg = high 150 overcurrent comparator i isen input bias current v isen = 0 to v isendis -1 a t leb leading edge blanking after v hvg and v lvg low- to-high transition 250 ns v isenx frequency shift threshold voltage rising (1) 0.76 0.8 0.84 v hysteresis voltage falling 50 mv v isendis latch off threshold voltage rising (1) 1.44 1.5 1.56 v td (h-l) delay to output 300 400 ns line sensing vth threshold voltage voltage rising or falling (1) 1.2 1.24 1.28 v i hys current hysteresis v line = 1.1 v 101316a v clamp clamp level i line = 1 ma 6 8 v
electrical characteristics l6599at 10/31 doc id 15534 rev 3 symbol parameter test condition min. typ. max. unit dis function i dis input bias current v dis = 0 to vth -1 a vth disable threshold voltage rising (1) 1.78 1.85 1.92 v oscillator d output duty cycle both hvg and lvg 48 50 52 % f osc oscillation frequency 58.2 60 61.8 khz r rfmin = 2.7 k 240 250 260 t d dead-time between hvg and lvg 0.2 0.3 0.4 s v cfp peak value 3.9 v v cfv valley value 0.9 v v ref voltage reference at pin 4 (1) 1.93 2 2.07 v i_ref = -2 ma (1) 1.8 2 2.2 v k m current mirroring ratio 1 a/a pfc_stop function i leak high level leakage current v pfc_stop =vcc, v dis = 0 v 1a r pfc_stop on-state resistance i pfc_stop = 1 ma, v dis = 1.5 v 130 200 v l low saturation level i pfc_stop = 1 ma, v dis = 1.5 v 0.2 v soft-start function i leak open-state current v(css) = 2 v 0.5 a r discharge resistance v isen > v isenx 120 standby function i dis input bias current v dis = 0 to vth -1 a vth disable threshold voltage falling (1) 1.2 1.24 1.28 v hys hysteresis voltage rising 50 mv delayed shutdown function i leak open-state current v(delay) = 0 0.5 a i charge charge current v delay = 1 v, v isen = 0.85 v 100 150 200 a vth 1 threshold for forced operation at max. frequency voltage rising (1) 1.98 2.05 2.12 v vth 2 shutdown threshold voltage rising (1) 3.35 3.5 3.65 v table 5. electrical characteristics (continued)
l6599at electrical characteristics doc id 15534 rev 3 11/31 symbol parameter test condition min. typ. max. unit vth 3 restart threshold voltage falling (1) 0.30 0.33 0.36 v low-side gate driver (voltages referred to gnd) v lvg l output low voltage i sink = 200 ma 1.8 v v lvg h output high voltage i source = 5 ma 12.8 13.3 v i sourcepk peak source current -0.3 a i sinkpk peak sink current 0.7 a t f fall time 30 ns t r rise time 60 ns uvlo saturation vcc= 0 to vcc on , i sink = 2 ma 1.1 v high-side gate driver (v oltages referred to out) v lvg l output low voltage i sink = 200 ma 1.8 v v lvg h output high voltage i source = 5 ma 12.8 13.3 v i sourcepk peak source current -0.3 a i sinkpk peak sink current 0.7 a t f fall time 30 ns t r rise time 60 ns hvg-out pull-down 25 k 1. values tracking each other table 5. electrical characteristics (continued)
application information l6599at 12/31 doc id 15534 rev 3 6 application information the l6599at is an advanced double-ended controller specifically designed for resonant half-bridge topology (see figure 4. ). in these converters the switches (mosfets) of the half-bridge leg are alternately switched on and off (180 out-of-phase) for exactly the same time interval. this is commonly referred to as operation at ?50% duty cycle?, although the real duty cycle, that is the ratio of the on-time of either switch to the switching period, is actually less than 50%. the reason is that there is an internally fixed dead-time t d inserted between the turn-off of either mosfet and the turn-on of the other, where both mosfets are off. this dead- time is essential for the converter to work correctly; it ensures soft- switching and enable high-frequency operation with high efficiency and low emi emissions. to perform output voltage regulation of the converter, the device is capable of operating in different modes ( figure 3 ), depending on the load conditions: 1. variable frequency at heavy and medium/ light load. a relaxation oscillator (see section 6.1: oscillator for more details) generates a symmetrical triangular waveform, to which the mosfets' switching is locked. the frequency of this waveform is related to a current that is modulated by the feedback circuitry. as a result, the tank circuit driven by the half-bridge is stimulated at a frequency dictated by the feedback loop to keep the output voltage regulated, thus exploiting its frequency-dependent transfer characteristics. 2. burst-mode control with no or very light load. when the load falls below a certain value, the converter enters a controlled intermittent operation, where a series of a few switching cycles at a nearly fixed frequency are spaced out by long idle periods where both mosfets are in an off-state. a further load decrease is translated into longer idle periods, and then into a reduction of the average switching frequency. when the converter is completely unloaded, the average switching frequency can go down to even a few hundred hertz, thus minimizing any magnetizing current losses as well as all frequency-related losses, and making it easier to comply with energy saving recommendations. figure 3. multi-mode operation of the l6599at !-v f sw 0 in 6ariable frequencymode 0inma x "urs t mode 6 in
l6599at application information doc id 15534 rev 3 13/31 figure 4. typical system block diagram 6.1 oscillator the oscillator is programmed ex ternally by means of a capacit or (cf) connected from pin 3 (cf) to ground, which is alternately charged and discharged by the current defined with the network connected to pin 4 (rf min ). the pin provides an accurate 2 v reference with about 2 ma source capability and the higher the cu rrent sourced by the pin, the higher the oscillator frequency. the block diagram in figure 5 shows a simplified internal circuit that explains the operation. the network that loads the rf min pin is generally made up of three branches: 1. a resistor rf min connected between the pin and ground, which determines the minimum operating frequency. 2. a resistor rf max connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side. while in operation, the phototransistor modulates the current through this branch - thus modulating the oscillator frequen cy - to perform output voltage regulation. the value of rf max determines the maximum frequency at which the half-bridge is operated when the phototransistor is fully saturated. 3. an r-c series circuit (css+rss) connec ted between the pin and ground that enables the setup of a frequency shift at startup (see section 6.3: soft-start ). note that the contribution of this branch is zero during steady-state operation. !-v 6 inac 6 outdc $!0 2esonant("isturnedoffincaseof 0&#gsanomalousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith energysavingregulations $!0 % ' $ ) 2 " & , ! ( 4 . ! . / 3 % 2 , ! . / ) 4 0 / 2 / 4 ! , 5 ' % 2 % 2 0 # & 0 $!0! 6 inac 6 outdc $!0 2esonant("isturnedoffincaseof 0&#gsanomalousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith energysavingregulations $!0 % ' $ ) 2 " & , ! ( 4 . ! . / 3 % 2 , ! . / ) 4 0 / 2 / 4 ! , 5 ' % 2 % 2 0 # & 0 $!0! ,! , 6 inac 6 outdc $!0 2esonant("isturnedoffincaseof 0&#gsanomalousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith energysavingregulations $!0 % ' $ ) 2 " & , ! ( 4 . ! . / 3 % 2 , ! . / ) 4 0 / 2 / 4 ! , 5 ' % 2 % 2 0 # & 0 $!0! 6 inac 6 outdc $!0 2esonant("isturnedoffincaseof 0&#gsanomalousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith energysavingregulations $!0 % ' $ ) 2 " & , ! ( 4 . ! . / 3 % 2 , ! . / ) 4 0 / 2 / 4 ! , 5 ' % 2 % 2 0 # & 0 $!0! ,!4 ,
application information l6599at 14/31 doc id 15534 rev 3 figure 5. oscillator internal block diagram the following approximate relati onships hold for the minimu m and the maximum oscillator frequency respectively: equation 1 after fixing cf in the hundred pf or nf range (consistent with the maximum source capability of the rf min pin and trading this off against the total consumption of the device), the value of rf min and rf max is selected so that the oscillato r frequency is able to cover the entire range needed for regulation, from the minimum value f min (at minimum input voltage and maximum load) to the maximum value f max (at maximum input voltage and minimum load): equation 2 a different selection criterion is given for r fmax in case burst-mode operation at no-load is used (see section 6.2: operation at no load or very light load ). 6 2&min #& 3 1 2 6 6 #& ) 2 q+ - q) 2 + - q) 2 2&min + - q) 2 2ss 2 &max #ss ,! 6 2&min #& 3 1 2 6 6 #& ) 2 q+ - q) 2 + - q) 2 2&min + - q) 2 2ss 2 &max #ss 6 2&min #& 3 1 2 6 6 #& ) 2 q+ - q) 2 + - q) 2 2&min + - q) 2 2ss 2 &max #ss ,!4 6 2&min #& 3 1 2 6 6 #& ) 2 q+ - q) 2 + - q) 2 2&min + - q) 2 2ss 2 &max #ss !-v () max min max min min rf // rf cf 3 1 f ; rf cf 3 1 f ? ? = ? ? = 1 f f rf rf ; f cf 3 1 rf min max min max min min ? = ? ? =
l6599at application information doc id 15534 rev 3 15/31 figure 6. oscillator waveforms and their relationship with gate-driving signals in figure 6 the timing relationship between the oscillator wave form and the gate-drive signal, as well as the swinging node of the half-bridge leg (hb) is shown. note that the low- side gate-drive is turned on while the oscillator's triangle is ramping up and the high-side gate-drive is turned on while the triangle is ramping down. in this way, at start-up, or as the ic resumes switching during burst-mode operation, the low-side mosfet is switched on first to charge the bootstrap capacitor. as a re sult, the bootstrap capacitor is always charged and ready to supply the high-side floating driver. 6.2 operation at no lo ad or very light load when the resonant half-bridge is lightly loaded or not loaded at all, its switching frequency is at its maximum value. to keep the output volt age under control in these conditions and to avoid losing soft-switching, there must be some significant residual current flowing through the transformer's magnetizing inductance. this current, however, produces some associated losses that prevent converter's no-load consumption from achieving very low values. to overcome this issue, the l6599at enables the designer to make the converter operate intermittently (burst-mode operation), with a se ries of a few switching cycles spaced out by long idle periods where both mosfets are in off-state, so that the average switching frequency can be substantially reduced. as a result, the average value of the residual magnetizing curr ent and the associated losse s is considerably cut do wn, thus facilitating the converter to comply with energy saving recommendations. the l6599at can be operated in burst-mode by using pin 5 (stby): if the voltage applied to this pin falls below 1.24 v the ic enters an idle state where both gate-drive outputs are low, the oscillator is stopped , the soft-start capacitor css keeps its charge and only the 2 v reference at rf min pin stays alive to minimize the ic's consumption and the v cc capacitor's discharge. the ic resumes normal operation as the voltage on the pin exceeds 1.24 v by 50 mv. to implement burst-mode operation the voltage applied to the stby pin needs to be related to the feedback loop. figure 7 a shows the simplest implementation, suitable for a narrow input voltage range (e.g. when there is a pfc front-end). !-v #& (6' t t ,6' t (" t 4 $ 4 $
application information l6599at 16/31 doc id 15534 rev 3 figure 7. burst-mode implementation: a) narrow input voltage range; b) wide input voltage range essentially, rf max defines the switching frequency f max above which the l6599at enters burst-mode operation. once fixed f max , rf max is derived from the relationship: equation 3 note that, unlike the f max considered in the previous section (? section 6.1: oscillator ?), here f max is associated to a load pout b greater than the minimum. pout b is such that the transformer's peak currents are low enough not to cause audible noise. the resonant converter's switching frequency, however, depends also on the input voltage. therefore, in cases where there is quite a large input voltage range with the circuit of figure 7 a, the value of pout b changes considerably. in this case it is recommended to use the arrangement shown in figure 7 b, where the information on the converter's input voltage is added to the voltage applied to the stby pin. due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction r a / (r a + r b ) needed to minimize the change of pout b . care should be taken to choose a total value of r a + r b that is much greater than r c to minimize the effect on the line pin voltage (see section 6.6: line sensing function ). whichever circuit is used, its operation can be described as follows. as the load falls below the value pout b the frequency tries to exceed the maximum programmed value f max and the voltage on the stby pin (v stby ) falls below 1.24 v. the ic then stops with both gate-drive outputs low, so that both mosfets of the half-bridge leg are in an off-state. the voltage v stby now increases as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.29 v, the ic starts switching again. after a while, v stby goes down again in response to the energy burst and stops the ic. in this way the converter works in a burst- mode fashion with a nearly constant switching frequency. a further load decrease then causes a frequency reduction, which can go down to even a few hundred hertz. the timing diagram of figure 8 illustrates this kind of o peration, showing the most significant signals. a small capacitor (typically in the hundred pf range) from the stby pin to ground, placed as close to the ic as possible to reduce switch ing noise pick-up, helps get clean operation. to help the designer meet energy saving re quirements even in power-factor-corrected systems, where a pfc pre-regulator precedes the dc-dc converter, the l6599at allows the pfc pre-regulator to be turned off during burst-mode operation, thereby eliminating the !-v d e '$3 67%< 5)plq 5 )plq 5 )pd[ '$3 67%< 5)plq 5 )plq 5 )pd[ /,1( 5 $ % 5 % 5 & 5 ' 5 $ 5 % !!5 & /$ /$ d e '$3 67%< 5)plq 5 )plq 5 )pd[ '$3 67%< 5)plq 5 )plq 5 )pd[ /,1( 5 $ % 5 % 5 & 5 ' 5 $ 5 % !!5 & /$7 /$7 1 f f rf 8 3 rf min max min max ? =
l6599at application information doc id 15534 rev 3 17/31 no-load consumption of this stage (0.5 1 w). there is no compliance issue because emc regulations on low-frequency harmonic emissions refer to nominal load, so no limit is imposed when the converter operates with light or no load. to do so, the l6599at provides pin 9 (pfc_stop): it is an open collector output, normally open, that is asserted low when the ic is idle during burst-mode operation. this signal is externally used for switching off the pfc controller and the pre-regulator as shown in figure 9 . when the l6599at is in uvlo the pin is kept open, to let the pfc controller start first figure 8. load-dependent operating modes: timing diagram figure 9. how the l6599at can switch off a pfc controller at light load 67%< 9 w i rvf p9 k\vwhu /9* +9* w w 3)&b6723 5hvrqdqw0rgh %xuvwprgh 5hvrqdqw0rgh 3)& *$7('5,9( !-v !-v ,! 0&#?34/0 ,! 6cc ).6 k a k a "# "# ,! 0&#?34/0 ,!3( 0&#?/+ !#?/+ ,!4 0&#?34/0 ,! 6cc ).6 k a k a "# "# ,!4 0&#?34/0 ,!3( 0&#?/+ !#?/+
application information l6599at 18/31 doc id 15534 rev 3 6.3 soft-start generally speaking, the purpose of soft-start is to progressively increase the converter's power capability when it is start ed up, so as to avoid excessiv e inrush curren t. in resonant converters the deliverable power depends inversely on frequency, so soft-start is attained by sweeping the operating frequency from an initial high value until the control loop takes over. with the l6599at, the converter's soft startup is easily achieved with the addition of an r-c series circuit from pin 4 (rf min ) to ground (see figure 10 , left). initially, capacitor c ss is totally discharged, so that the series resistor r ss is effectively parallel to rf min and the resulting initial fr equency is determined by r ss and rf min only, since the optocoupler's phototrans istor is cut off (as long as the output voltage is not too far from the regulated value): equation 4 the c ss capacitor is progressively charged until its voltage reaches the reference voltage (2 v) and, consequently, the current through r ss goes to zero. this typically takes 5 times constants r ss c ss . however, before this time interval completes, the ou tput voltage comes close to the regulated value and the feedback loop takes over, so that the optocoupler's phototransistor determines the operating frequency from that moment onwards. during this frequency sweep phase the operating frequency decays, following the exponential charge of c ss . that is, initially it changes re latively quickly but the rate of change gets slower and slower. this counteracts the non-li near frequency dependence of the tank circuit that makes the converter's po wer capability ch ange little as frequency is away from resonance, and change very quickly as the frequency approaches the resonance frequency (see figure 10 , right). figure 10. soft-start circuit (left) and power vs. frequency curve in a resonant half-bridge (right) as a result, the average input current increase s smoothly, without the peaking that occurs with linear frequency sweep, and the output volt age reaches the regulated value with almost no overshoot. typically, r ss and c ss are selected based on the following relationships: () ss min start r // rf cf 3 1 f ? ? = !-v ,!4 #ss 2&min 2 &min 2 33 # 33 2%3/.!.#% &2%15%.#9 f \:f \ )nitial frequency 3teady state frequency
l6599at application information doc id 15534 rev 3 19/31 equation 5 where f start is recommended to be at least 4 times f min . the proposed criterion for c ss is quite empirical and is a compromise between an effective soft-start action and an effective ocp (see next section). please refer to the timing diagram of figure 10 to see some significant signals during the soft-start phase. 6.4 current sense, ocp and olp the resonant half-bridge is e ssentially voltage-mode controlled; hence a current sense input only serves as overcurrent protection (ocp). unlike pwm-controlled converters, where energy fl ow is controlled by the duty cycle of the primary switch (or switches), in a resonant half -bridge the duty cycle is fixed and energy flow is controlled by its switchi ng frequency. this impacts the way current limitation can be realized. while in pw m-controlled converters energy flow can be limited simply by terminating switch conduction beforehand when the sensed current exceeds a preset threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half-bridge the switching frequency (that is, its oscillator freque ncy) must be increased an d this cannot be done as quickly as turning off a switch: it take s at least the next osc illator cycle to see the frequency change. this implies that to have an effective increase, capable of changing the energy flow significantly, the rate of change of the frequency must be slower than the frequency itself. this, in turn, implies that cycle-by- cycle limitation is no t feasible and that, therefore, the information on the primary current fed to the current sensing input must be somehow averaged. of course, the averaging time must not be too long, to prevent the primary current from reaching excessively high values. in figure 11 , a few current sensing methods are illu strated that are described in the following paragraphs. the circuit in figure 11 a is more simple, but the dissipation on the sense resistor rs may not be negligible, decreasing efficiency. the circuit in figure 11 b is more complex, but virtually lossless and recommended when the efficiency target is very high. ss 3 ss min start min ss r 10 3 c ; 1 f f rf r ? ? = ? =
application information l6599at 20/31 doc id 15534 rev 3 figure 11. current sensing techniques: a) with sense resistor, b) ?lossless?, with capacitive shunt the l6599at is equipped with a current sensing input (pin 6, isen) and a sophisticated overcurrent management system. the isen pin is internally connected to the input of a first comparator, referenced to 0.8 v, and to that of a second comparator referenced to 1.5 v. if the voltage externally applied to the pin by either circuit in figure 11 exceeds 0.8 v, the first comparator is tripped and this causes an intern al switch to be turned on and the soft-start capacitor c ss to be discharged (see section 6.3: soft-start ). this quickly increases the oscillator frequenc y and thereby limits energ y transfer. the discharge continues until the voltage on the isen pin has dropped by 50 mv; this, with an averaging time in the range of 10/f min , ensures an effective frequency rise. under output short-circuit, this operation results in a nearly constant peak primary current. it is normal that the voltage on the isen pin could overshoot the 0.8 v. however, if the voltage on the isen pin reaches 1.5 v, the second comparator is triggered and the l6599at shuts down and latches off with both the gate-drive outputs and the pfc_stop pin low, hence turning off the entire unit. the supply voltage of the ic must be pulled below the uvlo threshold and then again above the start-up level in order to restart. such an event may occur if the soft-start capacitor c ss is too large, preventing it from discharging fast enough, in cases of saturation of the transformer?s magnetizing inductance or a shorted secondary rectifier. in the circuit shown in figure 11 a, where a sense resistor rs in series with the source of the low-side mosfet is used, note the specific co nnection of the resonant capacitor. in this way, the voltage across rs is related to th e current flowing through the high-side mosfet and is positive most of the switching period, except for the time needed for the resonant current to reverse after the low-side mosfet has been switched off. assuming that the time constant of the rc filter is at least ten times the minimum switching frequency f min , the approximate value of rs can be found using the empirical equation: equation 6 where i crpkx is the maximum desired peak current flowing through the resonant capacitor and the primary winding of the transformer, which is related to the maximum load and the minimum input voltage. !-v d e '$3 ,6(1 t z i plq 5v &u 9vsn , &u '$3 ,6(1 &u 5 $ 5 % 1 & % & $ 1 t z i plq 9 &usn , &u /$ /$ d e '$3 ,6(1 t z i plq 5v &u 9vsn , &u '$3 ,6(1 &u 5 $ 5 % 1 & % & $ 1 t z i plq 9 &usn , &u /$7 /$7 crpkx crpkx crpkx pkx i 4 i 8 . 0 5 i vs rs ? =
l6599at application information doc id 15534 rev 3 21/31 the circuit shown in figure 11 b can be operated in two different ways. if the resistor r a in series to c a is small (not above a few hundred ohms, ju st to limit current spiking) the circuit operates like a capacitive current divider; c a is typically selected equal to cr/100 or less and is a low-loss type, and the sense resistor r b is selected as: equation 7 and c b is such that r b c b is in the range of 10 /f min . if the resistor r a in series with c a is not small (in this case it is typically sele cted in the ten k range), the circuit operates like a divider of the ripple voltage across the resonant capacitor cr, which, in turn, is related to its current through the reactance of cr. again, c a is typically selected equal to cr/100 or less, this time not necessarily a low-loss type, while r b (provided it is << r a ) according to: equation 8 where the reactance of c a (x ca ) and cr (x cr ) should be calculated at the frequency where i crpk = i crpkx . again, c b is such that r b c b is in the range of 10 /f min . whichever circuit is used, the calculated values of rs or r b should be considered preliminary values that may need to be adjusted after experimental verification. ocp is effective in limiting primary-to-secondary energy flow in case of an overload or an output short-circuit, but the output current through the secondary winding and rectifiers under these conditions might be so high that they endanger the converter?s safety if continuously flowing. to prevent any damage duri ng these conditions it is customary to force the intermittent operation of the converter, in order to bring the average output current to values such that the thermal stress for the transformer and the rectifiers can be easily handled. with the l6599at the designer can externally program the maximum time t sh that the converter is allowed to run overloaded or under short-circuit conditions. overloads or short- circuits lasting less than t sh do not cause any other action, hence providing the system with immunity to short duration phenomena. if, instead, t sh is exceeded an overload protection (olp) procedure is activated that shuts down the l6599at and, in cases of continuous overload/short-circuit, results in continuous intermittent operation with a user-defined duty cycle. ? ? ? ? ? ? ? ? + = a r crpkx b c c 1 i 8 . 0 r cr 2 c 2 a crpkx b x x r i 8 . 0 r a + =
application information l6599at 22/31 doc id 15534 rev 3 figure 12. soft-start and delayed shutdown upon overcurrent timing diagram this function is achieved with pin 2 (delay), by means of a capacitor c delay and a parallel resistor r delay connected to ground. as the voltage on the isen pin exceeds 0.8 v the first ocp comparator, in addition to discharging c ss , turns on an internal current generator that sources 150 a from the delay pin and charges c delay . during an overload/short-circuit the ocp comparator and the internal current source are repeatedly activated and c delay is charged with an average current that depends ess entially on the time co nstant of the current sense filtering circuit, on c ss and the characteristics of the resonant circuit. the discharge due to r delay can be neglected, considering that the associated time constant is typically much longer. this operation continues until the voltage on c delay reaches 2 v, which defines the t sh time. there is not a simple re lationship that links t sh to c delay , thus it is more practical to determine c delay experimentally. as a rough indication, with c delay = 1 f, t sh is in the order of 100 ms. once c delay is charged at 2 v the internal switch that discharges c ss is forced low continuously regardless of the ocp comparator?s output, and the 150 a current source is continuously on, until the voltage on c delay reaches 3.5 v. this phase lasts: equation 9 with t mp expressed in ms and c delay in f. during this time, the l6599at runs at a frequency close to f start (see section 6.3: soft-start ) to minimize the energy inside the resonant circuit. as the voltage on c delay is 3.5 v, the l6599at stops switching and the pfc_stop pin is pulled low. also, the internal generator is turned off, so that c delay is now slowly discharged by r delay . the ic restarts when the voltage on c delay is less than 0.3 v, which takes: equation 10 !-v w 9ff &vv w w '(/$< 67$5783 29(5 /2$' 29(5/2$' w 3ulpdu\ &xuuhqw 1250$/ 23(5$7,21 1250$/ 23(5$7,21 6+87'2:1 9 9rxw w $ 62)767$57 62)767$57 9 9 9 0,132:(5 w 3)&b6723 ,6(1 w 9 7 6+ 7 6723 7 03 7 vv delay mp c 10 t ? = delay delay 3 . 0 5 . 3 delay delay stop c r 5 . 2 ln c r t =
l6599at application information doc id 15534 rev 3 23/31 the timing diagram in figure 12 shows this operation. note that if during t stop the supply voltage of the l6599at (v cc ) falls below the uvlo threshold the ic retains memory of the event and does not restart immediately after v cc exceeds the start-up threshold if v(delay) is still higher than 0.3 v. also the pfc_stop pi n stays low as long as v(delay) is greater than 0.3 v. note also that in case there is an overload lasting less than t sh , the value of t sh for the next overload is lower if they are close to one another. 6.5 latched shutdown the l6599at is equipped with a comparator having the non-inverting input externally available at pin 8 (dis) and with the inverting input internally referenced to 1.85 v. as the voltage on the pin exceeds the internal threshold, the ic is immediately shut down and its consumption reduced at a low value. the information is latched and it is necessary to let the voltage on the v cc pin go below the uvlo threshold to reset the latch and restart the ic. this function is useful to implement latched overtemperature protection very easily by biasing the pin with a divider from an external reference voltage (e.g. pin 4, rf min ), where the upper resistor is an ntc physically loca ted close to a heating element like the mosfet, or the secondary diode or the transformer. an ovp can be implemented as well, e.g. by se nsing the output voltage and transferring an overvoltage condition via an optocoupler. 6.6 line sensing function this function basically stops the ic as the input voltage to the co nverter falls below the specified range and allows restart as the volt age goes back within the range. the sensed voltage can be either the rectified and filtered ma ins voltage, in which case the function acts as brownout protection or, in systems with a pf c pre-regulator front-end, the output voltage of the pfc stage, in which case the function serves as a power-on and power-off sequencing. l6599at shutdown upon input undervoltage is accomplished by means of an internal comparator, as shown in the block diagram of figure 13 , whose non-inverting input is available at pin 7 (line). the comparator is inte rnally referenced to 1.24 v and disables the ic if the voltage applied at the line pin is below the internal reference. under these conditions the soft-start is discharged, the pfc_stop pin is open and the consumption of the ic is reduced. pwm operation is re-ena bled as the voltage on the pin is above the reference. the comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 13 a current sink is on as long as the voltage applied at the line pin is below the reference and is of f if the voltage is above the reference. this approach provides an additional degree of freedom: it is possible to set the on threshold and the off threshold separately by properly choosing the resistors of the external divider (see below). with voltage hysteresis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator.
application information l6599at 24/31 doc id 15534 rev 3 figure 13. line sensing function: internal block diagram and timing diagram with reference to figure 11 , the following relationships can be established for the on (vin on ) and off (vin off ) thresholds of the input voltage: equation 11 which, solved for r h and r l , yield: equation 12 while the line undervoltage is active the start- up generator continues working but there is no pwm activity, thus the v cc voltage (if not supplied by anothe r source) continuo usly oscillates between the start-up and the uvlo thresholds, as shown in the timing diagram of figure 13 . as an additional measure of safety (e.g. in cases where the low-side resistor is open or missing, or in non-power factor corrected systems in cases of abnormally high input voltage) if the voltage on the pin exceeds 7 v, the l659 9at is shut down. if its supply voltage is always above the uvlo threshold, the ic restarts as the voltage falls below 7 v. the line pin, while the device is operating, is a high impedance input connected to high value resistors, thus it is prone to pick up no ise, which might alter the off threshold or give origin to undesired switch-off of the ic during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunction ing of this kind. if !-v ,!4 6in/+ (6)nputbus 6 ,).% 6cc 6 ?! 2 ( 2 , (6)nputbus 6in/+ 6cc 6in /. 6in /&& ,6' (6' 6out ,).% 6 ) (93 ?! t t t t t t t 6in/+ (6)nputbus 6 ,).% 6cc 6 ?! 2 ( 2 , (6)nputbus 6in/+ 6cc 6in /. 6in /&& ,6' (6' 6out ,).% 6 ) (93 ?! t t t t t t t l h off l 6 h on r 24 . 1 r 24 . 1 vin r 24 . 1 10 13 r 24 . 1 vin = ? + ? = ? ? 24 . 1 vin 24 . 1 r r ; 10 13 vin vin r off h l 6 off on h ? = ? ? = ?
l6599at application information doc id 15534 rev 3 25/31 the function is not used the pin must be connected to a voltage greater than 1.24 v but lower than 6 v (worst-case value of the 7 v threshold). 6.7 bootstrap section the supply of the floating high-side section is obtained by means of bootstrap circuitry. this solution normally requires a high voltage fast recovery diode (d boot , figure 14 a) to charge the bootstrap capacitor c boot . in the l6599at, a patented integrated structure replaces this external diode. it is achieved by means of a high voltage dmos, working in the third quadrant and driven synchronously with the low side driver (lvg), with a diode in series to the source, as shown in figure 14 b. figure 14. bootstrap supply: a) standard circuit; b) internal bootstrap synchronous diode the diode prevents any current flowing from the vboot pin back to v cc if the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. to drive the synchronous dmos a voltage higher than the supply voltage v cc is necessary. this voltage is obtained by means of an internal charge pump ( figure 14 b). the bootstrap structure introduces a voltage dr op while recharging cboot (i.e. when the low side driver is on), which increases with the operating frequency and with the size of the external power mos. it is the sum of the drop across the r (ds)on and the forward drop across the series diode. at low frequency this drop is very small and can be neglected but, as the operating frequency increases, it must be taken into account. in fact, the drop reduces the amplitude of the driving signal and can significantly increase the r (ds)on of the external high-side mosfet and then its conductive loss. this concern applies to converters designed with a high resonance frequency (indicatively, > 150 khz), so that they run at high frequency also at full load. otherwise, the converter runs at high frequency at light load, where the current flowing in the mosfets of the half-bridge leg is low, so that, generally, an r (ds)on rise is not an issue. however, it is wise to check this point anyway and the following equation is us eful to compute the drop on the bootstrap driver: !-v d e 287 9%227 9ff ' %227 & %227 '$3 287 9%227 9ff /9* & %227 /$ d e 287 9%227 9ff ' %227 & %227 '$3 287 9%227 9ff /9* & %227 /$7
application information l6599at 26/31 doc id 15534 rev 3 equation 13 where q g is the gate charge of the external power mos, r (ds)on is the on-resistance of the bootstrap dmos (150 w, typ.) and t charge is the on-time of the bootstrap driver, which equals about half the switching period minus the dead time t d . for example, using a mosfet with a total gate charge of 30 nc, the drop on the bootstrap driver is about 3 v at a switching frequency of 200 khz: equation 14 if a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be used, thus saving the drop on the r (ds)on of the internal dmos. f on ) ds ( e arg ch g f on ) ds ( e arg ch drop v r t q v r i v + = + = v 7 . 2 6 . 0 150 10 27 . 0 10 5 . 2 10 30 v 6 6 9 drop = + ? ? ? ? = ? ? ?
l6599at application information doc id 15534 rev 3 27/31 figure 15. application example: 90 w ac-dc adapter using l6563 and l6599at !-v 5 . 5 . 5 5 & 1 8 6)+$ & x)9 <;) / x & x)9 <;) & x)9 & 1 5 0 & 19 5 5 & 1 < 5 17&b5 6 & 1 & 1 ) )86( $ & 1; & 1; 9upv & x)9 4 67310)3 5 5 5 5 5 5 & 3) & x9 & x)9 5 . & 1 & x)9 5 0 5 0 5 5 5 . & 1 5 5 5 5 / $ ' // ' *%8- ' // ' 677+/ & 1 < - ,1387 &211 & 1 & 1 9#$ 5 . 5 . 5 . ' 1 5 5 5 . 5 . ' // 5 . 8 7/$,= / $& 4 6731.= 5 5 4 673 1.= 5 5 /9 * 1& &) 9%227 287 '(/$< /,1( +9* 9&& 67%< 5)plq *1' &66 ,6(1 ',6 3)&b6723 8 /$7 ' 6736/)3 ' 6736/)3 ' // & 3) & 1 5 0 5 0 5 . 5 0 5 0 5 . 5 . & x) & 1 & 1 5 . 5 . 5 . & x)9 <; ) ' %=9% 3:0b6723 =&' 08/7 9&& *1' &203 3)&b2. *' 581 9)) &6 3:0b/$7&+ ,19 7%2 8 / 5 . & 1 5 . & 1 5 5 5 5 & 3) 5 . 7 $$ 5 . & x)9 - 9 571 & 1 5 . & 1 5 . 5 . ' // ' // & 1 & 1 & 1) 5 0 5 0 4 674+ 1 . 5 ' // ' %=9 % 5 . 5 . 5 . 4 %& & 4 %&& ' %=9% 5 . ' %=9& 5 . 5 . 5 . 5 . 4 %&& 4 %& & 5 5 5 02817(' %< 5(:25.,1*
package mechanical data l6599at 28/31 doc id 15534 rev 3 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions an d product status are available at: www.st.com . ecopack is an st trademark. figure 16. dip16 mechanical data dip16 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 outline and mechanical data
l6599at package mechanical data doc id 15534 rev 3 29/31 figure 17. so16n mechanical data outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s8 (max.) (1) "d" and "f" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (.006inc.) so16 (narrow) 0016020 d
revision history l6599at 30/31 doc id 15534 rev 3 8 revision history table 6. document revision history date revision changes 05-jun-2009 1 initial release. 11-aug-2009 2 updated table 5 on page 9 30-oct-2009 3 updated table 5 on page 9
l6599at doc id 15534 rev 3 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L6599ATD

	To Download L6599ATD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .